1. Field of the Invention
The present invention relates to a semiconductor device which can control current conducting and inhibiting states by the voltage of a control electrode.
2. Description of the Background Art
FIG. 25 is a sectional view showing the structure of a conventional VDMOS 100, which is a semiconductor device controlling current conducting and inhibiting states by the voltage of a control electrode. An n.sup.- -type epitaxial layer 1 is provided on an upper surface of an n.sup.+ -type substrate 8, while p-type diffusion regions 2 are selectively formed on an upper surface of the n.sup.- -type epitaxial layer 1. Further, n.sup.+ -type diffusion regions 3 are selectively formed in the p-type diffusion regions 2.
A gate electrode 5 wrapped up in an oxide film 4 is provided above the upper surface of the n.sup.- -type epitaxial layer 1 and portions of the p-type diffusion regions 2 held between the n-type expitaxial layer 1 and the n.sup.+ -type diffusion regions 3. Further, a source electrode 6 is provided to be connected to the p-type diffusion regions 2 and the n.sup.+ -type diffusion regions 3 while being insulated from the gate electrode 5 by the oxide film 4. On the other hand, a drain electrode 7 is connected to the n.sup.+ -type substrate 8.
When the gate electrode 5 and the source electrode 6 are at the same potentials and the potential of the drain electrode 7 is increased with respect to that of the source electrode 6 in the VDMOS 100 having the aforementioned structure, reverse biases are applied across the p-type diffusion regions 2 and the n.sup.- -type epitaxial layer 1.
Therefore, depletion layers which are developed from the boundaries between the p-type diffusion regions 2 and the n.sup.- -type epitaxial layer 1 spread toward the n.sup.- -type epitaxial layer 1 to hold the voltage. Thus, the VDMOS 100 is held in an OFF state.
FIG. 26 illustrates the conventional VDMOS 100, in which the potential of the gate electrode 5 is increased with respect to the source electrode 6. Assuming that the source electrode 6 is grounded and positive potentials +V1 and +V2 are applied to the gate and drain electrodes 5 and 7 respectively, the surface regions of the p-type diffusion regions 2 held between the n.sup.+ -type diffusion regions 3 and the n.sup.- -type epitaxial layer 1 are n-inverted to form channels. Then, an electronic current Ie starts to flow from the source electrode 6 toward the drain electrode 7 through the channels. Thus, the VDMOS 100 enters a current conducting state (ON state).
When the potential of the gate electrode 5 is again reduced with respect to the source electrode 6, the channels formed in the surface regions of the p-type diffusion regions 2 held between the n.sup.+ -type diffusion regions 3 and the n.sup.- -type epitaxial layer 1 disappear to cut off the electronic current Ie, whereby the VDMOS 100 again enters an OFF state.
In the conventional semiconductor device having the aforementioned structure, the resistance (ON resistance) of the VDMOS 100 in an ON state is formed by a series resistance of channel resistances Rch developed in the channels, an accumulation resistance Ra developed in an accumulation layer which is formed in a portion of the n.sup.- -type epitaxial layer 1 close to the gate electrode 5, a JFET resistance Rj developed in a portion of the n.sup.- -type epitaxial layer 1 held between tile p-type diffusion regions 2, and an epitaxial resistance Repi developed along the cross direction of the n.sup.- -type epitaxial layer 1.
These resistances are explained in detail as follows: When the potential (V1) of the gate electrode 5 is increased with respect to the source electrode 6, n-type inversion layers are formed on surface portions of the p-type diffusion regions 2 which are held between the n.sup.- -type epitaxial layer 1 and the n.sup.+ -type diffusion regions 3 immediately under the gate electrode 5, by an influence from an electric field of the gate electrode 5. In such inversion layers, electrons flow along the surfaces of the p-type diffusion regions 2 to develop resistances, which are defined as the channel resistances Rch.
At this time, electrons are accumulated on a surface portion of the n.sup.- -type epitaxial layer 1 immediately under the gate electrode 5 by an influence from the electric field of the gate electrode 5, to form an accumulation layer. In this accumulation layer, electroils flow along the n.sup.- -type epitaxial layer 1 develop a resistance, which is defined as the accumulation resistance Ra.
When the potential (V2) of the drain electrode 7 is increased with respect to the source electrode 6, depletion layers extend from the p-type diffusion regions 2 toward the n.sup.- -type epitaxial layer 1. When electrons flow from a central portion of the surface portion of the n.sup.- -type epitaxial layer 1 which is held between the p-type diffusion regions 2 toward the drain electrode 7, such flow of the electrons is narrowed by the depletion layers. A resistance thus developed is defined as the JFET resistance Rj. In general, this indicates a resistance which is developed from the surface of the n.sup.- -type epitaxial layer 1 to the diffusion depths of the p-type diffusion regions 2.
The epitaxial resistance Repi is developed when electrons flow in the n.sup.- -type epitaxial layer 1. While portions located immediately under the p-type diffusion regions 2 have low electric current densities, the epitaxial resistance Repi substantially generally depends on the specific resistance, thickness and area of the n.sup.- -type epitaxial layer 1. A resistance of the n.sup.+ -type substrate 8 is so sufficiently lower than these resistances that the same is negligible.
The epitaxial resistance Repi depends on the specific resistance and thickness of the n.sup.- -type epitaxial layer 1, while the withstand voltage of the VDMOS 100 is also considerably influenced by the structure of this portion. When the specific resistance and thickness of the n.sup.- -type epitaxial layer 1 are reduced in order to reduce the ON resistance, the withstand voltage in an OFF state cannot be maintained at a high value.
On the other hand, it is possible to reduce the channel resistances Rch, the accumulation resistance Ra and the JFET resistance Rj by reducing the widths of the p-type diffusion regions 2 and the gate electrode 5, the depths of the p-type diffusion regions 2, and the like. However, since such a countermeasure also exerts an influence on the withstand voltage in an OFF state, it is necessary to optimize the process and designed dimensions.
Such optimization of the process and designed dimensions is restricted by the accuracy of a fabrication apparatus in the structure of the conventional semiconductor device, and it is difficult to further improve the characteristics.